Compound semiconductor structure

ABSTRACT

A method for fabricating semiconductor structure comprises the steps of providing a substrate including a first crystalline semiconductor material, patterning an opening in a dielectric layer above the substrate, the opening having a bottom, forming a crystalline interlayer on the substrate at least partially covering the bottom, and growing a second crystalline semiconductor material on the crystalline interlayer thereby at least partially filling the opening. The crystalline semiconductor materials are lattice mismatched, and the crystalline interlayer comprises an oxygen compound.

CROSS-REFERENCE TO RELATED PATENT APPLICATION(S)

The present application is a divisional application of U.S. Ser. No.14/467,660 filed Aug. 25, 2014. U.S. patent application Ser. No.14/467,660 claims priority to United Kingdom Application No. 1315208.7,filed Aug. 27, 2013, the entire contents of which are incorporatedherein by reference.

BACKGROUND OF THE INVENTION

This disclosure relates to a semiconductor structure, and moreparticularly to a semiconductor structure including crystalline compoundsemiconductor material grown on a crystalline semiconductor substratewherein the compound semiconductor material and the substratesemiconductor material are lattice mismatched. This disclosure alsoprovides a method of fabricating such a semiconductor structure.

Silicon is the basic material for present solid-state electronics, andprocessing techniques have been evolved for decennials. Hence, mostelectronic integrated circuit devices are based on silicon. However, therelatively low charge carrier mobility and its indirect band gap aredisadvantages and limit the use of silicon in particular inopto-electronic applications.

A monolithic integration of compound semiconductors on silicon wafers isdesirable and has extensively been investigated in the past. Severalproblems need to be overcome when compound semiconductors andconventional silicon technologies are to be combined. First, there is alarge lattice mismatch between a crystalline silicon substrate andcompound semiconductor crystals. Further, there is a thermal expansioncoefficient mismatch between the (silicon) wafer material and the activecompound semiconductor material. Additionally, a structural mismatchbetween diamond-like structures and zincblende structures may occur. Itis an overall goal to achieve high crystalline quality over variousmonolithic layers for compound semiconductor on a foreign substrate suchas silicon.

In an effort to achieve high crystalline quality in crystalline materiallayers that show a lattice mismatch, several methods have beendeveloped. For example, direct epitaxy of blanket layers allow for agradual transition from one lattice parameter to the next. However,relatively thick transition layers are needed to reduce the defectdensity considerably.

In US 2002/0153524 A1, a crystalline silicon substrate is provided witha perovskite stack comprising perovskite oxide materials. On the top ofthe stack, a crystalline material having a lattice mismatch with thesubstrate material is deposited. At the interface between the perovskitestack and the substrate, a strain relaxation occurs which reducesdefects in the top compound material.

Other techniques to combine compound semiconductor materials withconventional silicon wafers include bonding techniques. In direct waferbonding, a compound hetero structure is fabricated on a donor waferwherein the donor wafer material is eliminated after bonding with theconventional silicon wafer. This makes the bonding technology relativelyexpensive. Further, bonding is limited to the size of costly compoundsubstrate wafers.

Another approach for combining lattice-mismatched materials, such ascompound semiconductors with silicon substrates, is the aspect ratiotrapping approach. Aspect ratio trapping (ART) refers to a techniquewhere crystalline defects are terminated at non-crystalline, forexample, dielectric sidewalls. U.S. Pat. No. 8,173,551 B2 discloses amethod where a silicon substrate is covered with a dielectric layerdefining trenches through to the substrate material. In the trenches,epitaxial films of a compound material are deposited wherein particulargeometries of the growth front are realized. The aspect ratio of thetrenches needs to be large enough to terminate the defects that nucleateat the silicon-compound interface so that higher parts of thecrystalline compound show a low crystalline defect density. Someapproaches of the ART technique teach the use of Germanium microcrystalsgrown in silicon oxide trenches on a silicon substrate with a galliumarsenide film on top.

SUMMARY

Embodiments of the present invention include semiconductor structure, awafer structure comprising the semiconductor structure, and a method forfabricating the semiconductor structure. A semiconductor structurecomprises a substrate, a dielectric layer, a second crystallinesemiconductor material, and a crystalline interlayer. The substratecomprises a first crystalline semiconductor material. The dielectriclayer is located above the substrate and defines an open. The secondcrystalline semiconductor material at least partially fills the opening.The crystalline interlayer is between the substrate and the secondcrystalline semiconductor material. The first crystalline semiconductormaterial and the second crystalline semiconductor material are latticemismatched. The crystalline interlayer comprises an oxygen compound.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a schematic diagram of a first embodiment of asemiconductor structure.

FIG. 2 shows a schematic diagram of a semiconductor wafer includingembodiments of the semiconductor structure.

FIG. 3 shows a schematic diagram of a second embodiment of asemiconductor structure.

FIG. 4 shows a flow chart of method steps involved in a method forfabricating a semiconductor structure.

DETAILED DESCRIPTION

Silicon is the basic material for present solid-state electronics, andprocessing techniques have been evolved for decennials. Hence, mostelectronic integrated circuit devices are based on silicon. However, therelatively low charge carrier mobility and its indirect band gap aredisadvantages and limit the use of silicon in particular inopto-electronic applications. It would be advantageous to combine moresuitable semiconductor materials, such as III-V or IV-IV compoundsemiconductors, with silicon-based electronics on common siliconsubstrates.

It is, therefore, desirable to provide improved devices comprisinglattice mismatched crystalline semiconductor materials and methods forfabricating such.

It is an aspect of the present disclosure to provide improvedsemiconductor structures based on a crystalline semiconductor materialgrown on a crystalline semiconductor substrate wherein the semiconductormaterial and the substrate semiconductor material have a latticemismatch. The semiconductor material is in particular suitable forimplementing further devices. Other aspects relate to improved methodsfor fabricating such a semiconductor structure.

Accordingly, an embodiment of a first aspect of the invention relates toa semiconductor structure comprising a substrate, a dielectric layer, asecond crystalline semiconductor material, and a crystalline interlayer.The substrate comprises a first crystalline semiconductor material. Thedielectric layer is above the substrate defining an opening. The secondcrystalline semiconductor material at least partially fills the opening.The crystalline interlayer is between the substrate and the secondcrystalline semiconductor material. The first crystalline semiconductormaterial and the second crystalline semiconductor material arelattice-mismatched. The crystalline interlayer comprises an oxygencompound.

The semiconductor structure may comprise two different types ofcrystalline semiconductor materials and provides a crystalline systemsuitable for further processing, for example, for realizing electronicdevices. Some problems incurring with lattice-mismatched semiconductingmaterials are overcome by having the crystalline interlayer thatcomprises an oxygen compound. For example, oxides can be used ascrystalline interlayer materials.

Typically, developing defects at the interface between the first andsecond crystalline semiconductor material are directed towards theopening defining sidewalls in the dielectric layer. By providingoxygen-comprising interlayers at the bottom of the opening, a specificgrowth of the second crystalline semiconductor material in the openingoccurs. The specific growth that may proceed through island formation ina Volmer-Weber growth mode leads to less defects and a propagation ofthe defects only close to the bottom of the opening. The structuralrelationship between the oxide layer and the compound semiconductorlayer might also favor the reduction of interfacial defects whencompared to group IV and III-V.

The crystalline interlayer may comprise several functional layers. Forexample, the crystalline interlayer may include a stack of layers.

Embodiments of the semiconductor structure include a crystallinematerial of a first semiconductor material acting as a substrate with aforeign semiconductor material for forming active components. Theproposed semiconductor structure shows low defect densities preferablybelow 10⁷/cm².

In embodiments of the semiconductor structure, the dielectric layercovers the substrate at least partially. For example, the dielectriclayer is placed where the openings are defined. Similarly, thecrystalline interlayer covers at least partially the substrate where theopenings are defined. Hence, in the opening, an epitaxial growth of thesecond crystalline semiconductor material is performed.

Embodiments of the semiconductor structure comprise a crystallineinterlayer that is a crystalline oxide layer. The crystalline oxidelayer enhances the epitaxial growth of the second semiconductor materialthrough islands in a Volmer-Weber growth mode because of its poorwettability. Structural defect densities then occur where the islandscoalesce with each other, and the defect density decreases with thethickness or height of the second semiconductor material in the opening.

For example, the semiconductor structure may have an opening thatcomprises sidewalls and a bottom, wherein the bottom corresponds to asurface of the substrate. Preferably, the bottom is then covered withthe crystalline interlayer material comprising an oxygen compound.

The opening may be a trench. Further, a plurality of trenches oropenings can be provided so that crystalline regions are produced wherea foreign semiconductor material, as for example a compoundsemiconductor material, is placed above a conventional semiconductorsubstrate.

In embodiments of the semiconductor structure, the sidewalls of theopenings are non-crystalline. In particular, an amorphous material canbe used.

In embodiments of the semiconductor structure, an aspect ratio of thedepth to the width of the opening is at least one. In preferredembodiments, the aspect ratio is at least two and in particularlypreferred embodiments, the aspect ratio is larger than three. Generally,the density of crystalline defects propagating from the bottom of theopening upwards decreases. The defects decrease in the growth directionof the second semiconductor material as defects may terminate at thesidewalls and are directed in a lateral direction with respect to thegrowth direction.

In embodiments, the crystalline interlayer is a diffusion barrier layer.For example, certain crystalline oxides function as diffusion barrierlayers in addition to enhancing the nucleation of islands when growingthe second semiconductor material. In embodiments, the crystallineinterlayer has metallic conductivity. In embodiments, the semiconductorstructure may comprise crystalline interlayers that are ferroelectric.

Generally, the crystalline interlayer can include several layers or astack forming the crystalline interlayer. In embodiments, thecrystalline interlayer may include a metallic component, an insulatingcomponent, a ferroelectric component, a piezoelectric component, and/ora ferromagnetic component. Hence, the interlayer can be a multilayerstructure. One can contemplate of other functional properties of thecrystalline interlayer.

Preferably, the crystalline interlayer may separate neighboring trenchesor openings on a common the substrate electrically, i.e., thecrystalline interlayer includes an insulating (sub-) layer. Further, thecrystalline interlayer may prevent substrate material from diffusinginto the eventually grown second crystalline semiconductor material,i.e., the crystalline interlayer includes a diffusion barrier (sub-)layer.

In embodiments of the semiconductor structure, the substrate comprises afirst crystalline semiconductor material including a silicon substrateoriented along the (001) direction.

Further, a wafer structure comprising a plurality of semiconductorstructures as mentioned before is proposed. For example, a wafer cancomprise a plurality of trenches which are overgrown with compoundsemiconductor material wherein the interface between the wafer materialand the epitaxial overgrown compound material is at least partiallygiven by a crystalline oxide material.

According to an embodiment of another aspect of the invention, a methodfor fabricating a semiconductor structure is disclosed. Embodiments ofthe method comprise the steps of providing a substance, defining anopening, forming a crystalline interlayer, and growing a secondcrystalline semiconductor material. The substrate provided includes afirst crystalline semiconductor material. The opening is definite in adielectric layer above the substrate and the opening has a bottom. Thecrystalline interlayer is formed on the substrate and at least partiallycovers the bottom. The second crystalline semiconductor material isgrown on the crystalline interlayer, thereby at least partially fillingthe opening. The first crystalline semiconductor material and the secondcrystalline semiconductor material are lattice-mismatched. Thecrystalline interlayer comprises an oxygen compound.

In particular, the fabricated semiconductor structure displays featuresand aspects as explained with respect to the embodiments of thesemiconductor structure above.

The proposed method for fabricating a semiconductor structure can beimplemented employing conventional semiconductor technologies. Alsoaspects of the ART technique can be employed.

Embodiments of the method comprise the additional step of forming thedielectric layer on the substrate. For example, the substrate may beprovided in terms of a wafer, and the dielectric layer is deposited orgenerated through conventional techniques.

The method may further comprise the step of forming the dielectric layeron the crystalline interlayer. The sequence of the above-mentionedmethod steps can be adopted accordingly. One may first form thecrystalline interlayer and then deposit the dielectric layer prior todefining the openings or trenches. However, one may as well first formtrenches in the dielectric, amorphous layer wherein the trenches reachthe substrate material and after that form the crystalline interlayer.

For example, an opening is defined in the dielectric layer, therebyforming sidewalls of the opening. The method may also comprise providingor forming a plurality of openings in the form of trenches. The step ofdefining the opening can be performed after forming the crystallineinterlayer.

In embodiments of the method, growing the second crystallinesemiconductor material on the crystalline interlayer comprises formingislands of said second crystalline semiconductor material on thecrystalline interlayer. As an example, the growth of the secondcrystalline semiconductor material may occur according to a Volmer-Webergrowth mode due to the poor wettability of the surface of thecrystalline interlayer comprising oxygen. Then, the method may furthercomprise coalescing the islands, thereby forming an epitaxial film ofthe second crystalline semiconductor material.

The method may be adapted to form only one single island per opening ortrench in the step of growing a second crystalline semiconductormaterial on the crystalline interlayer, e.g., the dimension of theopening can be realized accordingly. Reducing the number of islands thatpotentially merge decreases the number of defects due to the coalescenceof islands.

In embodiments of the method, the step of overgrowing the opening withthe second crystalline semiconductor material, thereby filing theopening, is performed.

The method may also comprise the step: after filling the opening withthe second crystalline semiconductor material, planarizing overgrownsecond semiconductor material.

Optionally, the method may comprise further processing the secondcrystalline semiconductor material for fabricating electronic or opticaldevices.

For example, an embodiment of a semiconductor structure comprises asemiconductor substrate, an amorphous layer at least partially coveringthe substrate, and at least one opening formed in the amorphous layer.The opening has side walls and a bottom. The bottom of the opening is atleast partially covered with a crystalline oxide layer. A compoundsemiconductor material is in the opening on the crystalline oxide layer.

An embodiment of a method for forming this embodiment of a semiconductorstructure may comprise the steps of providing a semiconductor substrate,forming an amorphous layer at least partially covering the substrate,and defining at least one opening in the amorphous layer. The openinghas side walls and a bottom. At least part of the bottom of the openingis covered with a crystalline oxide layer. A compound semiconductormaterial is applied in the opening on the crystalline oxide layer.

The compound semiconductor material of the channel region preferablyincludes a III-V compound semiconductor material, a II-VI compoundsemiconductor material, and/or a IV-IV compound semiconductor material.For example, the compound semiconductor material isIn_(x)(Ga,Al)_((1-x))As where 0<x<1, InP, GaP, InSb, GaSb, ZnSe, CdTe,SiC, SiGe and/or GaN. In particular, InGaAs and/or GaAs has a highercarrier mobility than silicon and allows for fast semiconductor devices.

In some embodiments of the semiconductor structure, the compoundsemiconductor material is replaced by germanium (Ge). Although, Ge isstrictly not a compound semiconductor, the disclosed features for asemiconductor structure and the methods may also hold for Ge-baseddevices.

Certain embodiments of the presented semiconductor structure and themethod for fabricating a semiconductor structure may comprise individualor combined features, method steps, or aspects as mentioned above orbelow with respect to exemplary embodiments.

FIG. 1 shows a schematic diagram of an embodiment of a semiconductorstructure 1. The general semiconductor structure 1 can be part of asemiconductor device or an integrated circuit chip. The semiconductorstructure 1 comprises a crystalline substrate 2, a dielectric layer 3with an opening 4 having sidewalls 5, 6 and a bottom 7. The bottom 7 iscovered with a crystalline interlayer 8 comprising an oxygen compound.The opening 4 is filled with a second crystalline semiconductor material9 that is lattice mismatched to the semiconductor material of thecrystalline substrate 2.

The crystalline substrate 2, for example, is a crystalline semiconductoror a compound semiconductor wafer of a large diameter. The wafer can be,for example, a material from group IV of the periodic table. Materialsof group IV include, for example, silicon, germanium, mixed silicon andgermanium, mixed silicon and carbon, mixed silicon germanium and carbon,and the like. For example, the crystalline substrate 2 corresponds to acrystalline silicon wafer that is used in the semiconductor industry.For example, the crystalline substrate 2 can be a miscut silicon (001)substrate. A crystalline silicon wafer in the orientation (001) mayreduce dislocations and results in an improved quality of subsequentlygrown layers on the crystalline substrate 2.

Above the crystalline substrate 2, the dielectric layer 3, for example anon-crystalline amorphous material, is formed having a thickness d. Thedielectric layer 3 can be formed by known methods, as for examplethermal oxidation, chemical vapor deposition (CVD), plasma enhanced CVD(PECVD), atomic layer deposition, chemical solution deposition, MOCVD,evaporation, sputtering, and other like deposition processes. Examplesof such dielectric material include, but are not limited to, SiO₂,Si₃N₄, Al₂O₃, AlON, Ta₂O₅, TiO₂, La₂O₃, SrTiO₃, LaAlO₃, ZrO₂, Y₂O₃,Gd₂O₃, MgO, MgNO, Hf-based materials, and combinations includingmultilayers thereof.

The dielectric layer 3, for example an amorphous layer, defines anopening 4. The opening 4 may be in the form of a trench having a bottom7 and sidewalls 5, 6. The bottom 7 of the opening 4 or trench is atleast partially covered with a crystalline oxygen compound. For example,this crystalline interlayer 8 can comprise a crystalline perovskiteoxide material. The crystalline interlayer 8 acts as a nucleation layer,so that subsequent crystalline growth of compound material in theopening 4, for example a trench, is enhanced. The crystalline interlayer8 acts also as a diffusion barrier between the substrate material andthe second crystalline semiconductor material 9 (i.e., a potentiallyactive compound material).

The crystalline interlayer 8 may comprise an alkaline earth metaltitanate, as for example, barium titanate (BaTiO₃), strontium titanate(SrTiO₃), barium strontium titanate (Sr_(z)Ba_(1-z)TiO₃), or anothersuitable perovskite oxide material. The crystalline interlayer 8 caninclude metal oxides, such as alkaline earth metal zirconates, alkalineearth metal halfnates, alkaline earth metal tantalates, alkaline earthmetal ruthenates, alkaline earth metal niobates, alkaline earth metalvanadates, perovskite oxides, such as alkaline earth metal tin-basedperovskites, lanthanum aluminate, lanthanum scandium oxide, andgadolinium oxide. Also, various nitrides could be used as interlayermaterials, such as gallium nitride, aluminum nitrides, and boronnitride. The interlayer can be conductive, as for example, strontiumruthenate. The crystalline interlayer 8 preferably includes anycombinations of the before-mentioned materials including multilayersthereof.

Preferably, the crystalline interlayer 8 includes a multilayer structureor a layer stack. This allows to combine, for example, insulatingproperties for separating the trenches electrically from each other andproviding a suitable seed or nucleation layer for the subsequent growthof the second crystalline semiconductor material 9 (i.e., the secondsemiconductor layer). Isolating the openings 4 (i.e., the trenches) fromeach other facilitates the fabrication of electronic or other devices onthe same crystalline substrate 2 (i.e., a wafer).

In embodiments, BaTiO₃ having piezo- and/or ferro-electric properties isused as an interlayer material. BaTiO₃ is MBE grown.

The opening 4, or trench, is filled with a second crystallinesemiconductor material 9 (i.e., a compound material). Due to thecrystalline interlayer 8, the growth of a second crystallinesemiconductor material 9 that is lattice-mismatched to the substratematerial is simplified. In particular, defects due to the latticemismatch are more or less contained to the lower region in the bottom ofthe opening 4 or trench.

The second crystalline semiconductor material 9 may comprise a compoundsemiconductor which can be selected as needed for a particularsemiconductor structure from any type of IIIA and VA elements (III-Vsemiconductor compounds), mixed III-V compounds, group II (A or B) andVIA elements (II-VI semiconductor compounds), and mixed II-VI compounds.Examples include gallium arsenide (GaAs), gallium indium arsenide(GaInAs), gallium aluminum arsenide (GaAlAs), indium phosphide (InP),cadmium sulfide (CdS), cadmium mercury telluride (CdHgTe), zinc selenide(ZnSe), zinc sulfur selenide (ZnSSe), lead selenide (PbSe), leadtenoride (PbTe), lead sulfide selenide (PbSSe), and the like. However,the crystalline material in the openings 4 or trenches can also compriseother semiconductor materials, metals, or non-metal materials which areused in the formation of semiconductor structures, devices, and/orintegrated circuits.

The width w of the opening 4 is preferably smaller than the depth d ofthe opening 4 or trench or the height of the second crystallinesemiconductor material 9. Due to the lattice mismatch at the interfacewhen epitaxially growing the second crystalline semiconductor material9, i.e., the compound material, on the crystalline interlayer 8, or acrystalline oxide interlayer, show crystalline defects. However, thosedefects occur only at the bottom 7 and stop at the opening walls 5, 6,or trench walls, in the amorphous material of the dielectric layer 3.The semiconductor structure 1, shown in FIG. 1, can be further processedfor grating active electronic components in the second crystallinesemiconductor material 9, i.e., the compound material.

FIG. 2 shows a schematic diagram of a semiconductor wafer 100 includinga plurality of semiconductor structures similar to the one shown inFIG. 1. FIG. 3 shows a schematic diagram of a second embodiment of sucha semiconductor structure 10 which is highlighted as an insert in FIG.2. FIG. 2 shows a semiconductor wafer 100, as for example, aconventional 300 mm crystalline substrate 2, i.e., a silicon wafer, as asubstrate. The crystalline substrate 2, i.e., a substrate material, iscovered with a crystalline interlayer 8, i.e., a crystalline oxygencompound, as for example, barium titanate. The silicon substrate is, forexample, a Si (001) substrate.

In embodiments, a barium titanate film is epitaxially deposited onto thesubstrate surface 2A, and the film may range between 5 and 20 nm, forexample. The semiconductor wafer 100, i.e., a wafer structure, comprisesan amorphous dielectric layer, for example, a silica (SiO₂) layer thatcan be deposited by chemical vapor deposition (CVD) or anotherdeposition technique. Other methods for forming, for example, amorphousoxide layers on the crystalline interlayer 8, can be contemplated. Thedielectric layer 3, i.e., an amorphous layer, comprises openings 4 ortrenches having a high aspect ratio, i.e., the depths of the respectiveopening 4 or trench is larger than its width. The openings 4 or trenchesare filled with a compound material, as for example, a gallium arsenidecompound.

The openings 4 (see FIG. 3) or trenches are patterned by any appropriatetechnique, as for example, by forming a mask, such as a photoresistmask, over the crystalline substrate 2, the crystalline interlayer 8,and a dielectric layer 3. The mask can be patterned to expose at least aportion of the dielectric layer 3. Next, the exposed portion of thedielectric layer 3 is removed, for example, by reactive ion etching todefine the openings 4 or trenches. The trench then reaches to thesurface of the crystalline interlayer 8.

Therefore, as can be seen in FIG. 3, the opening 4 or trench comprisessidewalls 5, 6 and a bottom 7 that corresponds to the crystalline oxidecompound as a crystalline interlayer 8. The crystalline interlayer 8 is,for example, barium titanate having a perovskite structure. The secondcrystalline semiconductor material 9, i.e., a compound semiconductormaterial, filling the openings 4 or trenches can be formed by selectiveepitaxial growth in any suitable deposition system. For example, metalorganic chemical vapor deposition (MOCVD), atmospheric pressure CVD, lowor reduced pressure CVD, ultra-high vacuum CVD, molecular beam epitaxy(MBE), or atomic layer deposition (ALD) techniques can be employed. Anepitaxial overgrowth of the openings 4 or trenches may occur asindicated in FIG. 2 for the semiconductor structures 11, 12. An optionalstep of planarizing the overgrown compound material can be performed.

Turning now to FIG. 3, aspects of a method for fabricating thesemiconductor structure 10 are explained. FIG. 4 shows an exemplaryflowchart of method steps that are involved in fabricating asemiconductor structure 10.

For example, the silicon substrate in its (001) orientation is providedin a first step S1.

Next, on the surface 2A of the crystalline substrate 2, i.e., asemiconductor substrate, a perovskite material, such as barium titanate,is epitaxially grown as an interlayer in step S2. Investigations of theapplicant have shown that perovskite-type barium titanate can be grownby molecular bean epitaxy with radio frequency sputtering in a verycontrolled fashion. The thickness of the interlayer is, for example,between 1 and 100 nm, preferable between 5 and 20 nm. The bariumtitanate retains the crystalline structure and shows piezo- andferroelectric properties.

Next, a silica layer is deposited on the crystalline interlayer 8. Thisdielectric layer 3 can have a thickness between 1 and 500 nm. Forexample, the thickness is about 200 nm. For example, the dielectriclayer is formed by a method known in the art, e.g., plasma-enhancedchemical vapor deposition in step S3.

Next, the openings 4 or trenches are patterned into the dielectric layer3, i.e., an amorphous layer, in step S4. The trenches have a high aspectratio, i.e., d>w.

After defining the opening 4, the second crystalline semiconductormaterial 9 is grown in step S5, i.e., the opening 4 or trench is filledwith a second crystalline semiconductor material 9, i.e., a epitaxiallygrown compound material, such as gallium arsenide. The secondcrystalline semiconductor material 9, i.e., a gallium arsenide material,nucleates as islands on the crystalline interlayer 8, i.e., a perovskitematerial, at the bottom of the trench, i.e., at the surface 7A, islandsof gallium arsenide grow in a Volmer-Weber mode and coalesce to a film.Any defects that occur during the crystal growth essentially propagateplanary and stop at the boundary to the sidewalls 5, 6 at the dielectriclayer 3, i.e., an amorphous material. Hence, the crystalline interlayer,i.e., a perovskite layer or interlayer, acts as an additional trappinglayer for crystal defects due to lattice mismatches as well as adiffusion barrier between the crystalline substrate 2, i.e., a siliconmaterial, and the second crystalline semiconductor material 9, i.e., anactive compound material, in the opening 4 or trench. The epitaxialgrowth of the gallium arsenide or any other compound material is, forexample, done by CVD with an RF heating. The crystalline defects, suchas threading dislocation, stacking false twin boundaries, andanti-boundaries are substantially eliminated to the upper portion of thematerial in the opening 4 or trench. A clean and high-qualitycrystalline material is obtained that can be further processed forfabricating, for example, photonic or electronic devices. This isindicated in FIG. 3 as box 13.

The disclosed semiconductor structures can be part of a semiconductorchip. The resulting integrated circuit chips can be distributed by thefabricator in raw wafer form (that is, as a single wafer that hasmultiple unpackaged chips), as a bare die, or in a packaged form. In thelatter case the chip is mounted in a single chip package (such as aplastic carrier, with leads that are affixed to a motherboard or otherhigher level carrier) or in a multichip package (such as a ceramiccarrier that has either or both surface interconnections or buriedinterconnections). In any case, the chip is then integrated with otherchips, discrete circuit elements, and/or other signal processing devicesas part of either an intermediate product, such as a motherboard, or anend product. The end product can be any product that includes integratedcircuit chips, ranging from toys and other low-end applications toadvanced computer products having a display, a keyboard or other inputdevice, and a central processor.

What is claimed is:
 1. A method for fabricating semiconductor structurecomprising: providing a substrate including a first crystallinesemiconductor material; patterning an opening in a dielectric layerabove the substrate, the opening having a bottom; forming a crystallineinterlayer on the substrate at least partially covering the bottom; andgrowing a second crystalline semiconductor material on the crystallineinterlayer thereby at least partially filling the opening; wherein: thefirst crystalline semiconductor material and the second crystallinesemiconductor material are lattice mismatched; and the crystallineinterlayer comprises an oxygen compound.
 2. The method of claim 1,further comprising forming the dielectric layer on the substrate.
 3. Themethod of claim 1, further comprising forming the dielectric layer onthe crystalline interlayer.
 4. The method of claim 1, wherein theopening is patterned in the dielectric layer thereby forming sidewallsof the opening.
 5. The method of claim 1, wherein the step of patterningthe opening is performed after forming the crystalline interlayer. 6.The method of claim 1, wherein growing the second crystallinesemiconductor material on the crystalline interlayer comprises formingislands of said second crystalline semiconductor material on thecrystalline interlayer.
 7. The method of claim 6, further comprisingcoalescing the islands thereby forming an epitaxial film.
 8. The methodof claim 1, wherein growing the second crystalline semiconductormaterial on the crystalline interlayer comprises forming a single islandof said second crystalline semiconductor material on the crystallineinterlayer in the opening.
 9. The method of claim 1, further comprisingovergrowing the opening with the second crystalline semiconductormaterial thereby filling the opening.
 10. The method of claim 9, furthercomprising, after filling the opening with the second crystallinesemiconductor material, planarizing overgrown second crystallinesemiconductor material.
 11. The method of claim 1, further comprisingprocessing the second crystalline semiconductor material for fabricatingelectronic or optical devices.